1. Field of the Invention
The present invention relates to very high frequency phase locked loops (PLLs) and, in particular, to techniques for generating a phase step in a continuous stream of data to test the response of a digital phase locked loop.
2. Discussion of the Related Art
The "testability" of an integrated circuit (IC) is a characteristic that effects the cost of the IC. Design of an IC for testability allows the status of the device to be determined, faults within the device to be isolated and device performance to be observed.
In the past, the testability of a phase locked loop (PLL) has included the generation of a phase step in the continuous stream of input data to the PLL. As shown in FIG. 1, the generation of a phase step in a continuous stream of data (Data.sub.-- in) requires a programmed delay line 10 and a high speed multiplexer 12 for selecting data with a known phase shift based upon a select input signal (Phase.sub.-- Select) to the multiplexer 12. The phase-shifted signal (Data.sub.-- out) from the multiplexer 12 is provided to the data recovery PLL 14. The dynamic of the real time phase step response of the PLL 14 is observed using a phase meter 16, which is an instrument that converts any phase displacement into a corresponding voltage.
However, when the data rate exceeds 100 Mbits per second, the generation of a phase step in the input data to test the response of the PLL becomes a challenge requiring the design of a custom phase step generator.
Commonly-assigned U.S. Pat. No. 5,224,125, issued Jun. 29, 1993, discloses a signed phase-to-frequency (P-to-F) converter for use in a very high frequency PLL. Referring to FIG. 2, the quasi-digital, high frequency PLL 20 disclosed in the '125 patent includes a digital phase detector 22, a signed P-to-F converter 24, a 3-phase ring oscillator 26 and a frequency controlled oscillator (FCO) 28. FCO 28 and P-to-F converter 24 allow the use of a clock frequency which is no higher than the generating frequency of the PLL 20 to achieve acceptable phase resolution.
The P-to-F converter 24 converts the phase error information generated by the phase detector 22, which is in the form of UP, DOWN and HOLD signals, to multi-phase analog waveforms (PHASE 1, PHASE 2, PHASE 3) that are used to drive the FCO 28. The output frequency of the P-to-F converter 24 determines the locking range of the PLL 20. The phase error direction, either plus or minus, is represented by the phase relationship, either leading or lagging, of the multi-phase outputs of the P-to-F converter 24, which the FCO 28 interprets as either an increase, a decrease or no change in the operating frequency.
As shown in FIG. 3, the P-to-F converter 24 disclosed in the '125 patent includes a counting circuit 30 that converts the plus/minus phase error signal UD.sub.-- PI provided by the phase detector 22 to a 7-bit count signal. The three most significant bits (MSB) of the count signal, i.e., the HI.sub.-- CNT signal, are used by a 3-phase waveform generator 32 to generate a 3-phase sawtooth pattern. The four least significant bits (LSB) of the count signal, i.e., the LO.sub.-- CNT signal, are utilized by a pulse density modulation (PDM) circuit 34 to generate a signal that indicates the binary weight of the LSB part of the count. The output of the LSB PDM circuit 34 and the 3-phase sawtooth pattern are applied to three MSB PDM circuits 36, 38, 40. The three carry outputs of the MSB PDM circuits 36, 38, 40 are the digital outputs of the P-to-F converter 24. Following buffering, the three digital outputs of the P-to-F converter 24 are converted to analog signals (PHASE 1, PHASE 2, PHASE 3) by RC filters. The plus/minus phase is indicated by the leading/lagging phase relationship among the output waveforms.
U.S. Pat. No. 5,224,125 is hereby incorporated by reference in its entirety.
A problem associated with the solution disclosed in the '125 patent is real time delay. That is, since generation of the 3-phase triangular waveform is within the PLL tracking loop, the time required for synthesis directly impacts upon the response time of the phase error correction, which increases the phase jitter of the recovered clock.
Commonly-assigned U.S. Pat. No. 5,646,967, issued Jul. 8, 1997 to Wong Hee and Gabriel Li, provides an improvement over the PLL system disclosed in the '125 patent.
Referring to FIG. 4, the '967 patent discloses a triangular waveform synthesizer 42 for a phase-to-frequency converter that generates a multi-phase triangular waveform using both Pulse Density Modulation (PDM) and a DC modulation scheme. The lower counter 44, upper counter 46 and lower PDM circuit 48 are similar to those utilized in the FIG. 3 waveform synthesizer. However, to minimize both delay and logic, while continuing to provide reasonable resolution, a 4-bit upper PDM circuit 50 and associated logic generates the PDM output waveform with polarity information and two switching waveforms that encode the DC level information to provide a resultant sum. The resulting waveform, after filtering, is the triangular waveform. Since the switching and adding of the DC levels occur in real time, the actual delay for the resultant triangular wave is only that of the 4-bit upper PDM circuit 50.
U.S. Pat. No. 5,646,967 is hereby incorporated by reference in its entirety.
The system disclosed in the '967 patent improves upon the system disclosed in the '125 patent. Both systems take advantage of Pulse Density Modulation techniques. The key advantage of the system disclosed in the '967 patent over the system disclosed in the '125 patent is its simplicity and short real time delay, which, as stated above, is a major factor in reducing the output jitter of the PLL.
A problem with the system disclosed in the '967 patent, however, is the relatively high energy of the third and higher harmonics of the triangular wave.
Commonly-assigned U.S. Pat. No. 5,651,036, issued Jul. 22, 1997 to Wong Hee and Gabriel Li, provides an improvement over both of the above-described systems.
Referring to FIG. 5, the '036 patent discloses a phase-to-frequency converter 52 that utilizes a triangular waveform synthesizer to generate a multi-phase triangular waveform using both Pulse Density Modulation (PDM) and a DC modulation scheme. The lower counter 54, upper counter 56, lower PDM circuit 58 and upper PDM circuit 60 are similar to those utilized in the FIG. 4 triangular waveform synthesizer. That is, a PDM and associated logic generates both the multi-phase PDM output waveform with polarity information and two switching waveforms that encode the DC level information to provide a resultant sum. The resulting waveform, after filtering, is the triangular waveform. However, as shown in FIG. 5, a wave modifier 62 modifies each triangular waveform by reducing the ramp rate at appropriate positions to suppress the third harmonic and its multiples. The ramp rate is proportional to the output of the Pulse Density Modulator. The rate of the PDM output is reduced by gating the output by the wave synthesizer clock signal, thereby reducing the density of the output by one half in the appropriate positions.
U.S. Pat. No. 5,651,036 is hereby incorporated by reference in its entirety.
Although the '036 patent discloses a PLL that substantially improves over the prior art, the response time of the PLL can still be improved.
Above-cited Related application Ser. No. 08/873,118 discloses a trapezoidal waveform synthesizer that converts a digital phase error signal into a plurality of phase-separated trapezoidal analog waveforms. The trapezoidal waveform synthesizer includes an up/down counter that counts the positive and negative phase errors and generates a multi-bit, parallel digital counter output signal that indicates a cumulative current value of the phase errors. The counter output signal includes a least significant bit (LSB) portion and most significant bit (MSB) portion. An upper PDM circuit converts the MSB portion of the counter output signal and a portion of the LSB portion of the counter output signal to a plurality of sets of serially-weighted multi-bit output signals. A lower PDM circuit converts the MSB and LSB portions of the counter output signal to a plurality of serially-weighted single-bit output signals. Each one of the sets of multi-bit outputs and a corresponding one of the single-bit outputs are provided to an RC circuit that converts the digital signal to an analog voltage. The waveform synthesizer thereby provides a plurality of phase-separated trapezoidal waveforms.